Because of process, power supply, and temperature variations, integrated circuits may vary in the speed at which they operate. CMOS integrated circuits may vary by factors of five or more in the speed at which they operate. The integrated circuit design engineer must design for and simulate the effects of these variables. In addition, the engineer who then uses the integrated circuit must also be concerned about unequal propagation delays between two or more identical integrated circuits. Another problem which arises is that of accurate delay lines integrated into a CMOS integrated circuit. With speed variations of five or more, a delay line must be long enough to provide the necessary delay at a best case speed situation. However, for the worst case speed situation, the delay line is five times longer than necessary, wasting valuable area and affecting yields.
One solution to the delay line problem is the use of commercially available external delay lines connected to the CMOS integrated circuit. Another solution is to use NMOS technology where integrated delay lines are available, but at a cost in power consumption. An NMOS integrated delay line works by altering the load at the output of cross-coupled NOR gates, which requires the use of a two-phase clock system. The effect is to require a relatively large amount of circuit area dedicated to the delay line in an NMOS integrated circuit.
A solution for CMOS integrated circuits is to use a CMOS inverter with a transistor connected in series between the inverter and VDD, and a second transistor connected in series between the inverter and ground. A voltage is applied to these two series transistors to cause them to alter the rise and fall time of the CMOS inverter circuit. This circuit is best described with respect to FIG. 1 below. The amounts of voltage needed to control the rise and fall times to cause a specific amount of delay is generated by a digital phase-locked loop circuit as described below with respect to FIG. 2, which is similar to the circuit of U.S. Pat. 4,899,071 issued Feb. 6, 1990 to Morales. The prior art circuit of FIG. 2, however, has a limitation in that the intrinsic delay naturally occurring in the inverter circuits causes a delay in addition to that generated by the phase-locked loop. The minimum resolution of the circuit is thus determined by adding the intrinsic delay of 10 each inverter circuit to the amount of delay needed to calibrate the phase-locked loop. This value will always be greater than the slowest uncompensated intrinsic delay for a given process. This intrinsic delay also becomes a significant factor when the delay circuits are used to form a delay line.
There is need in the art then for a circuit to produce a control signal that has been compensated for the intrinsic delay within the circuit producing the voltage. There is further need in the art for a delay line circuit that compensates for the intrinsic delay in the circuits and allows for higher resolution than the resolution provided by the uncompensated intrinsic delay of a series of CMOS inverters.